VLSI Design Engineer
VLSI Design Engineer - A fast track to the success.
100% Placement Assistance | 1000+ Hiring Partners
Rated 4.5 out of 5
4587 Learners Enrolled
Program Duration : 570 Hrs
At 15 - 20 hrs/week
Classroom Based
Learning format
Branches Across India
Select your Preferred Branch
About Program
VLSI Design Engineers specialize in creating advanced integrated circuits (ICs) with a focus on performance, power, and area efficiency. They excel in both front-end and back-end design, using sophisticated tools to develop complex digital and analog circuits. Their expertise drives innovation in industries like consumer
electronics, telecommunications, and automotive, making them invaluable to technology companies and research institutions.
Audience
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B.E./ B.Tech. – Computer Science, IT, Electronics or equivalent
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BCA, BSc Computer Science, MCA and MSc Computer Science
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Working Professional in IT looking for upskilling
Key Benefits
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Comprehensive Learning
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Practical Skills
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Industry-Relevant
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Career Advancement
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Flexibility
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Updated Knowledge
Course Curriculum
- Introduction to Number Systems, Logic Gates
- Understanding Combinational Logic Circuit Designing -Adder, Subtractor, MUX, DEMUX, Encoder and Decoder etc
- Understanding Sequential Logic Circuit DesigningLatches, Flipflops, Counter, Register etc
- Introduction to Finite state machine (FSM)
- Moore’s Machine and Mealy’s Machine.
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- Need, Scope, Use and History of VLSI
- Introduction to Chip Design Process
- Description of Hardware Description Languages
- Applications of VLSI
- VLSI Design Flow
- Moore’s Laws
- VLSI Design Flow and YChart
- Front-Back End VLSI Design
- Overview of Digital Design with Verilog HDL Evolution of CAD
- Emergence of HDLs, typical HDL-based design flow
- Why Verilog HDL, trends in HDLs.
- Hierarchical Modeling Concepts
- Top-down and bottom-up design methodology
- Differences between modules and module instances
- Parts of a simulation, design block, stimulus block
- Basic Concepts Lexical conventions
- Data types, system tasks, compiler directives
- Modules and Ports Module definition
- Port declaration, connecting ports
- Hierarchical name referencing
- Gate-Level Modeling
- Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise
- Fall and tum-off delays, min, max, and typical delays. Dataflow Modeling
- Continuous assignments
- Delay specification, expressions, operators, operands, operator types
- Behavioural Modeling Structured procedures
- Initial and always, blocking and nonblocking statements
- Delay control, Event control
- Conditional statements, multiway branching loops, sequential and parallel blocks
- Tasks and Functions
- Differences between tasks and functions
- Declaration, invocation
- Useful Modeling Techniques
- Procedural continuous assignments
- Overriding parameters
- Conditional compilation and execution
- Introduction to FPGA
- Architecture
- FPGA Input/output Blocks (IOBs), Special FPGA Functions
- Logic Synthesis, FPGA Programming with Verilog Basics, Tool Training
- Different Voltage Requirements for FPGA
- Different External Memory Devices Architecture
- IO Planning, Report Analysis for Timing, Area and Power
- CPLD, FPGA Working, References, Design Flow, Design Tricks
- H/W Components on FPGA Board and Their Working
- Designing Basic FPGA Examples (Adder, Subtractor, Counter etc.)
- Introduction to IC Technology
- Basic Electrical Properties of MOS and BiCMOS Circuits
- IDS – VDS Relationships
- MOS Transistor Threshold Voltage
- Figure of Merit, Transconductance
- Pass Transistor NMOS Inverter, Various Pull-Ups
- CMOS Inverter Analysis and Design
- Bi-CMOS Inverters
- Fabrication Process Flow
- Transmission Gates etc
- Device Sizing, Timing Parameters
- Estimation of Layout Resistance & Capacitance
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- VLSI Design Flow
- MOS Layers
- Stick Diagrams, Design Rules and Layout
- Lambda (λ)-based Design Rules for Wires, Contacts and Transistors
- Layout Diagrams for NMOS and CMOS Inverters and Gates
- Scaling of MOS Circuits, Limitations of Scaling
- Introduction to Simulation Tools
- Place and Route Extraction, LVS
- Netlist to GDS-II Flow
- Device Generator Libraries
- SPICE Modelling, SPICE Tutorials and Commands
- Sources and Passive Components
- Inverter Transient
- Introduction to UVM
- Introduction to OVM
- Need for File Interchange
- GDS2 Stream
- Caltech Intermediate Format (CIF)
- Library Exchange Format (LEF)
- Design Exchange Format (DEF)
- Standard Delay Format (SDF)
- DSPF
- SPEF
- Advance Library Format (ALE)
- Waves Waveform and Vector Exchange
- Specification
- Physical Design Exchange Format
- Open Access
Tools & Softwares
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Branches Across India
- Bangalore
- Electronic City
- Nelamangala
- Ramnagar
- Belagum
- Kolar
- Chikballapur
- Udupi
- Haveri
- Nellore
- Chennai
- Kolhapur
- Gaya
- Nalanda
- Nawada
- Aurangabad
- Sangli
- Osmanabad
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